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NTD18N06L Power MOSFET
18 Amps, 60 Volts, Logic Level N-Channel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features
V(BR)DSS 60 V
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RDS(on) TYP 54 mW@5.0 V ID MAX 18 A (Note 1)
* Pb-Free Packages are Available
Typical Applications
* * * *
Power Supplies Converters Power Motor Controls Bridge Circuits
G
N-Channel D
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 10 MW) Gate-to-Source Voltage - Continuous - Non-repetitive (tpv10 ms) Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C - Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 2) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 1.0 mH, IL(pk) = 12 A, VDS = 60 Vdc) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1) - Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "15 "20 4 18 10 54 55 0.36 2.1 -55 to +175 72 Adc Apk W W/C W C mJ 4 DPAK-3 CASE 369D STYLE 2 C/W RqJC RqJA RqJA TL 2.73 100 71.4 260 C 18N6L A Y WW 1 2 3 123 Gate Drain Source Device Code = Assembly Location = Year = Work Week AYWW 18N6L 12 3 2 1 3 Drain Gate Source 4 Drain DPAK CASE 369C STYLE 2 Unit Vdc Vdc Vdc S
MARKING DIAGRAMS
4 Drain AYWW 18N6L
TJ, Tstg EAS
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR-4 board using the minimum recommended pad size. 2. When surface mounted to an FR-4 board using the 0.5 sq in drain pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
August, 2004 - Rev. 3
Publication Order Number: NTD18N06L/D
NTD18N06L
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 3) (VGS = 5.0 Vdc, ID = 9.0 Adc) Static Drain-to-Source On-Resistance (Note 3) (VGS = 5.0 Vdc, ID = 18 Adc) (VGS = 5.0 Vdc, ID = 9.0 Adc, TJ = 150C) Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 9.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge Ga e C a ge (VDS = 48 Vdc, ID = 18 Adc, Vdc Adc VGS = 5.0 Vdc) (Note 3) 50 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage Reverse Recovery Time e e se eco e y e (IS = 18 Adc, VGS = 0 Vdc, Adc Vdc dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. (IS = 18 Adc, VGS = 0 Vdc) (Note 3) (IS = 18 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR - - - - - - 0.94 0.83 41 26 15 0.057 1.15 - - - - - mC Vdc ns s (VDD = 30 Vdc, ID = 18 Adc, Vd Ad VGS = 5.0 Vdc, 5 0 Vdc RG = 9.1 W) (Note 3) td(on) tr td(off) tf QT Q1 Q2 - - - - - - - 9.9 79 19 38 11 3.2 6.5 20 160 40 80 22 - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc 1.0 f = 1 0 MHz) Ciss Coss Crss - - - 482 166 56 675 230 80 pF VGS(th) 1.0 - RDS(on) - VDS(on) - - gFS - 1.0 0.86 13.5 1.3 - - mhos 54 65 Vdc 1.8 5.2 2.0 - Vdc mV/C mW V(BR)DSS 60 - IDSS - - IGSS - - - - 1.0 10 100 nAdc 70 57.6 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
ORDERING INFORMATION
Device NTD18N06L NTD18N06LG NTD18N06L-1 NTD18N06L-1G NTD18N06LT4 NTD18N06LT4G Package DPAK DPAK (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) DPAK DPAK (Pb-Free) Shipping 75 Units/Rail 75 Units/Rail 75 Units/Rail 75 Units/Rail 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NTD18N06L
40 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V 8V 30 6V 20 4.5 V 5.5 V 5V
40 VDS 10 V 30
4V 3.5 V 3V
20
10
10
TJ = 25C TJ = 100C TJ = -55C 3.2 4 4.8 5.6
0
0
1
2
3
4
0 1.6
2.4
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.12 VGS = 5 V 0.1 0.08 0.06 0.04 0.02 0 TJ = 25C TJ = 100C
0.12 VGS = 10 V 0.1 0.08 TJ = 100C 0.06 TJ = 25C 0.04 TJ = -55C 0.02 0
TJ = -55C
0
10
20
30
40
0
10
20
30
40
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Gate-to-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 -50 -25 1 0 25 50 75 100 125 150 175 0 10000 ID = 9 A VGS = 5 V IDSS, LEAKAGE (nA) 1000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
VGS = 0 V TJ = 150C
100 TJ = 100C 10
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTD18N06L
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
1400 Ciss 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 Crss 10 15 20 25 Coss Crss Ciss VDS = 0 V VGS = 0 V TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NTD18N06L
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 8 1000
6 t, TIME (ns) QT 4 Q1 Q2 VGS 100 tr tf td(off) 10 2 ID = 18 A TJ = 25C 0 0 2 4 6 10 8 QG, TOTAL GATE CHARGE (nC) 12 1 1 10 RG, GATE RESISTANCE (W) 100 td(on) VDS = 30 V ID = 18 A VGS = 5 V
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
20 IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C
16
12
8
4
0 0.6 0.68 0.76 0.84 0.92 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTD18N06L
SAFE OPERATING AREA
EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D, DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C 10 100 ms 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 10 ms dc 10 ms 80 ID = 12 A 60
40
20
0 25 175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1.0 D = 0.5
0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (ms) P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
0.01 1.0E-05
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NTD18N06L
PACKAGE DIMENSIONS
DPAK CASE 369C-01 ISSUE O
-T- B V R
4 SEATING PLANE
C E
DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
A S
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTD18N06L
PACKAGE DIMENSIONS
DPAK-3 CASE 369D-01 ISSUE B
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
B V R
4
Z A
3
S -T-
SEATING PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTD18N06L/D

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